Power semiconductor devices, including lateral diffused metal-oxide semiconductor (LDMOS) devices, are employed in a wide variety of applications, such as, for example, power amplification and switching. Although these power devices can achieve high efficiency, linearity and power gain with sufficient reliability when biased at relatively high drain bias voltages (e.g., up to about 30 volts), it is desirable to increase a power density (PDEN) in theses devices. Increased power density generally results in smaller device areas, which translates into lower cost per watt. Furthermore, increasing the power density without also increasing parasitic capacitances and inductances per unit device width typically results in lower overall parasitics for the same output power, which is critical for matching, power gain and efficiency. LDMOS devices, when employed as high-speed, high-voltage switches, for example, generally require a substantially low on-resistance (e.g., less than a few ohms). Power density and on-resistance (Ron) are related in that both characteristics require a device having a drain structure that can support a high current density (e.g., about several milliamperes (mA)).
There exists a trade-off in conventional power semiconductor devices between on-resistance and breakdown voltage (VBD), as discussed, for example, in a paper by M. Amato, entitled “Comparison of Lateral and Vertical DMOS Specific On-resistance,” Proceedings of IEEE IEDM, pp. 736-739 (1985), the disclosure of which is incorporated by reference herein. The relationship between the breakdown voltage of a given device and the on-resistance multiplied by the area of the device (Ron×A) is typically used as an efficiency metric for gauging the electrical performance characteristics of power transistors.
Many high performance power devices employ a reduced surface field (RESURF) principle to some extent in order to improve a tradeoff between increased HCI degradation and decreased breakdown voltage (see, e.g., A. Ludikhuize, “A Review of RESURF Technology,” Proceedings of IEEE ISPSD, pp. 11-18, May 2000, the disclosure of which is incorporated by reference herein). RESURF is a well-known technique employed in the design of high voltage, low on-resistance devices. In lateral power devices in which drain current (ID) flows predominantly along a silicon surface of the device, a lateral field is created in a drift region of the device which acts in the direction of the drain current. HCI degradation, which can significantly limit the performance of a device, particularly when operating the device with a high drain bias voltage, is generally strongly related to a magnitude of this lateral drift region field. Basically, the RESURF effect distributes electric field potential lines in the device at least in part by introducing a vertical field component into the drift region which helps to balance the drift region charge so as to reduce a curvature of the potential in the drift region field. This results in a more uniform distribution of the electric field at breakdown, compared to a device which does not utilize RESURF, thereby increasing a breakdown voltage of the device.
While it is known to optimize a device for breakdown voltage, an undesirable amount of HCI degradation in the device often results. Likewise, conventional methodologies for reducing HCI degradation in the device often undesirably decrease the breakdown voltage of the device. HCI degradation can significantly limit the performance and/or reliability of the device, particularly when operating the device at high drain bias voltages. As is well known, the HCI phenomenon generally results from heating and subsequent injection of charge carriers into a gate oxide and/or an oxide layer above a drift region of an LDMOS device. This injection of charge carriers often results in a localized and nonuniform buildup of interface states and oxide charges near and underneath a gate and/or in the drift region of the device. It has been shown that, over time, several electrical characteristics of the LDMOS device degrade as a direct result of HCI (see, e.g., S. Manzini et al., “Hot-Electron-Induced Degradation in High-Voltage Submicron DMOS Transistors,” Proc. IEEE ISPSD, pp. 65-68, 1996, which is incorporated by reference herein). For example, HCI can produce variations in certain characteristics of the LDMOS device, including saturation current, threshold voltage, transconductance, on-resistance, etc., thus undesirably affecting the performance and/or reliability of the device.
There exists a need, therefore, for a metal-oxide semiconductor (MOS) device having improved power density, particularly when biased at a high drain voltage, that does not suffer from one or more of the problems exhibited by conventional MOS devices. Moreover, it would be desirable if the improved MOS device was compatible with existing integrated circuit (IC) fabrication process technologies.